1. Field of the Invention
This invention relates to insulated gate field effect transistors (IGFETS) and more particularly to the reduction of parasitic bipolar effects, including "latchup", in complementary metal oxide semiconductor (CMOS) circuits by reducing the resistance across the source-substrate and source-well junctions.
2. Prior Art
It is well known that parasitic lateral and vertical bipolar transistors are formed in CMOS circuits. Further, recently the phenomenon of "latchup" due to regenerative thyristor action between the vertical and lateral parasitic bipolar transistors has been studied and various solutions proposed. For example, Satou et al in U.S. Pat. No. 4,167,747 proposed various methods to prevent the initial activation of the parasitic thyristor including increasing the base width of one or both of the 4,035,826 proposed providing low resistance contacts to the substrate of an IGFET by providing doped conductive paths to the substrate which contact the surface through and within the boundaries of the IGFET source region. Stevenson in U.S. Pat. No. 4,173,767 proposed sinking a deep region in the epitaxial substrate of a CMOS and doping the deep region with the opposite conductivity type of the epitaxial substrate. The deep region is to be located between the respective drains of the CMOS. Bhatia et al in U.S. Pat. No. 3,955,210 proposed guard rings of the same conductivity type as the channel type of the respective MOSFET as a means to drain off parasitic bipolar collector current thereby preventing latchup.
Payne, et al ("Elimination of Latch-up in Bulk CMOS", 1980 IEDM, Pages 248-251) suggested the addition of an N+ surface diffusion tied to V.sub.DD in an N-substrate and placed adjacent one source of a CMOS, and a P+ diffusion tied to V.sub.SS in a P-well and placed adjacent the other source of the CMOS, as a means of reducing lateral potential buildup in the CMOS.
Each of the above proposed solutions continues to present difficulties. Increasing the base width of the lateral or vertical parasitic transistors increases bulk and/or reduces component density. Gold is a well known contaminant of semiconductor processing equipment and it would be preferable to devise a method for reducing CMOS latchup which does not involve doping the substrate with gold and, likewise, it is preferable to devise a structure for reducing CMOS latchup which is not doped with gold. Providing conductive paths through the source region of a CMOS which are doped opposite the source region doping, entails critical masking steps and could increase source surface area which would reduce component density in IC's. Similarly, the solution suggested by Payne, et al increases lateral source dimensions.
Furthermore, a primary concern in preventing latchup is reducing the voltage drop resulting from unwanted current injected through CMOS drains exiting the CMOS at points distant from the injection site. One method of reducing the voltage drop is to bring the injection site and exit point into close proximity. At a minimum, the structure proposed by Payne et al requires current injected through a drain to travel the entire width of a MOSFET'S corresponding source region to reach the exit point. Reducing this travel distance further would increase the probability of preventing latchup due to the unwanted injected current. Also, Stevenson's and Bhatia's solutions require an additional doped region between MOSFETS thereby again impeding high density IC's as well as requiring further processing.
Another area conservative problem in CMOS devices is presented by the past use of doped ohmic contact region adjacent or separated by a small distance from each source in the CMOS. One ohmic contact was typically heavily doped with the same conductivity type as the well and the other ohmic contact was typically heavily doped with the same conductivity type as the substrate. These ohmic contacts were connected to the supply and negative (or ground) voltages to hold the substrate and well at the same potentials as the source regions therein. This in turn kept the source-well and source-substrate junctions unbiased thus preventing unwanted minority carrier injection across these junctions. Often, guard rings which are placed around the respective MOSFETS of the CMOS to isolate the MOSFETS from one another can perform this additional task of ohmic contacts to the well and substrate.
Use of such extra ohmic contacts and/or guard rings clearly reduced potential component density in IC's. Elimination of these extra ohmic contacts while still keeping the source-well and source-substrate junctions unbiased under normal operating conditions would allow increased component density in IC's.